Various programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), include configuration memory that may be loaded with configuration data for specific applications. In certain PLDs, the configuration memory may be volatile in nature. As such, the configuration data may be loaded into the configuration memory from another non-volatile memory, such as a flash memory, in response to appropriate instructions or when the PLD is powered up.
It is desirable that the configuration data loaded into the configuration memory corresponds to a valid data pattern that facilitates meaningful operation of the PLD. If invalid configuration data is accidentally loaded into the configuration memory, contention errors may cause the PLD to operate improperly or suffer damage.
One approach to determining the validity of configuration data involves the use of a single validation bit in the non-volatile memory. In this approach, as part of an erase process, all bits of the non-volatile memory may be pre-programmed with a particular logic state corresponding, for example, to a logical high state. The non-volatile memory is then erased (corresponding, for example, to a logical low state) and additional conventional operations associated with the erasure of non-volatile memories may be performed. Subsequently, the non-volatile memory is loaded with configuration data. Following the loading, the validation bit may be programmed to a logical high state again to indicate a successful loading of the configuration data.
Unfortunately, if a power failure occurs during the pre-programming operation, the validation bit may be erroneously left at the logical high state which falsely indicates that a valid configuration data pattern has been loaded into the non-volatile memory. As a result, an invalid configuration data pattern may be inadvertently loaded into the volatile configuration memory of the PLD when power is restored.
In certain applications, users may wish to ensure that valid configuration data is provided in non-volatile memory of the PLD, but may also wish to control whether the configuration data is loaded into configuration memory when the PLD is powered up. Unfortunately, where a single validation bit is used as in the prior approach identified above, configuration data may be automatically loaded into configuration memory whenever the PLD is powered on and the validation bit has been programmed to a logical high state. As a result, users may be unable to prevent the loading of configuration data into configuration memory when desired for particular applications.
Accordingly, there is a need for an improved approach to the loading of configuration data that reduces the risk of inadvertent loading of invalid or corrupted configuration data into configuration memory, and that provides users with additional control over the loading.